Introduction to Compute Express Link™ (CXL™) Technology

3-Second Blueprint (English)

1. CXL runs over the PCIe 5.0 physical layer to create a unified, low-latency cache-coherent memory space across CPUs and accelerators.
2. Three protocols divide tasks: CXL.io handles discovery, CXL.cache lets devices cache host RAM, and CXL.mem enables host load/store access.
3. Devices span Type 1 coherent NICs, Type 2 GPUs with shared device memory, and Type 3 memory buffers for DRAM capacity expansion.