Instruction Pipeline Architecture

3-Second Blueprint (English)

1. Instruction pipelining overlaps fetch, decode, operand read, and execute stages across clock cycles to increase CPU instruction throughput.
2. Conditional or unconditional branch instructions redirect the program counter only after decoding, invalidating sequentially fetched ops.
3. Hardware interrupts and taken branches force a pipeline stall that flushes in-flight stages and restarts fetching from the target address.