Branch in a Pipeline - Georgia Tech - HPCA: Part 1

3-Second Blueprint (English)

1. PC-relative conditional branches compare registers in the ALU stage, leaving two intervening clock cycles before the jump outcome is known.
2. Canceling two speculatively fetched instructions on a mispredicted branch raises its effective cost from one cycle to three pipeline cycles.
3. Because waiting unconditionally wastes two slots every time, CPUs must predict branch targets during Fetch using only the instruction PC.